基于FPGA数字锁相环源程序代码(已验证运行-超值)(共5页).doc

精选优质文档-倾情为你奉上基于FPGA数字锁相环源程序代码（已验证运行，超值）module dpll_top (fin,fout,clk,reset,Kmode);input fin,clk; /clk时钟100ns(10MHZ）input reset; /reset高电平复位，enable高电平有效input 2:0 Kmode; /滤波计数器的计数模值设定output fout; /fout是锁频锁相输出reg fout;reg 8:0 Ktop; reg 8:0Count;wire inc,dec;reg dnup;reg inc_new,dec_new,inc_pulse,dec_pulse;reg delayed,advanced,Tff;reg IDout;reg 14:0 count_N; reg 15:0 cnt; reg cnt_en;reg load;wire cnt_clr;/2.异或门鉴相器模块always (fin or fout)begin dnup=finfout;end /3.K模计数器模块always (Kmode) begin case(Kmode) 3'b001:Ktop<=7; 3'b010:Ktop<=15; 3'b011:Ktop<=31; 3'b100:Ktop<=63; 3'b101:Ktop<=127; 3'b110:Ktop<=255; 3'b111:Ktop<=511; default:Ktop<=15; endcase end /根据鉴相器输出的加减控制信号dnup进行可逆计数器的加减运算always (posedge clk or posedge reset)begin if(reset) Count<=0; else if(!dnup) begin if(Count=Ktop) Count<=0; else Count<=Count+1; end else begin if(Count=0) Count<=Ktop; else Count<=Count-1; end end /输出进位脉冲carry和借位脉冲borrowassign inc=!dnup&(Count=Ktop);assign dec=dnup&(Count=0);/4.脉冲增减模块always (posedge clk)begin if(!inc) begin inc_new<=1; inc_pulse<=0; end else if (inc_pulse) begin inc_new<=0; inc_pulse<=0; end else if (inc&&inc_new) begin inc_pulse<=1; inc_new<=0; end else begin inc_pulse<=0; inc_new<=0; endend always (posedge clk)begin if(!dec) begin dec_new<=1; dec_pulse<=0; end else if (dec_pulse) begin dec_new<=0; dec_pulse<=0; end else if (dec&&dec_new) begin dec_pulse<=1; dec_new<=0; end else begin dec_pulse<=0; dec_new<=0; endend always(posedge clk)begin if (reset) begin Tff<=0; delayed<=1;advanced<=1; end else begin if (inc_pulse) begin advanced<=1;Tff<=!Tff; end else if(dec_pulse) begin delayed<=1; Tff<=!Tff; end else if (Tff=0) begin if(!advanced) Tff<=!Tff; else if(advanced) begin Tff<=Tff; advanced<=0; end end else begin if (!delayed) Tff<=!Tff; else if(delayed) begin Tff<=Tff;delayed<=0; end end end endalways (clk or Tff)begin if (Tff) IDout=0; else begin if(clk) IDout=0; else IDout=1; endend /5.N分频参数控制模块always (posedge fin)/fin上升沿到的时候，产生各种标志以便后面控制 begin if (reset) begin cnt_en=0; load=1; end else begin cnt_en=cnt_en; load=cnt_en; end endassign cnt_clr=(fin & load);always (posedge clk or negedge cnt_clr) begin if (!cnt_clr) cnt=0; else if (cnt_en) begin if (cnt=65536) cnt=0; else cnt=cnt+1; end endalways (posedge load) begin count_N=cnt/2; /这里取fin周期的一半 end/6.N分频器模块integer count; always(posedge IDout) if(reset) begin fout=0; count=0; end else begin if(count>=(count_N/2)-1) begin fout<=fout;count<=0;end else count<=count+1; endendmodule专心-专注-专业